1. Field of the Invention
The present invention relates to an improvement of evaluation of an output signal of a Device Under Test (DUT) in response to an input signal provided by an Automated Test Equipment (ATE) to said DUT.
2. Description of Prior Art
Integrated Circuits (IC) generally need to be tested to assure proper operation. This—in particular—is required during IC development and manufacturing. In the latter case, the ICs are usually tested before final application. During test, the IC, as Device Under Test (DUT), is exposed to various types of stimulus signals, and its responses are measured, processed and usually compared to an expected response of a good device. Automated Test Equipments (ATE) usually perform these tasks according to a device-specific test program. Examples for ATE are the Agilent 83000 and 93000 families of Semiconductor Test Systems of Agilent Technologies as disclosed e.g. under http://www.ate.agilent.com/ste/products/intelligent_test/SOC_test/SOC_Tech Oview.shtml. Details of those families are also disclosed e.g. in EP-A-859318, EP-A-864977, EP-A-886214, EP-A-882991, EP-A-1092983, U.S. Pat. No. 5,499,248, U.S. Pat. No. 5,453,995.
According to the prior art a clocked comparator is used for comparing the voltage level of the output signal of the DUT at the ATE input against a threshold level at a predetermined point in time within the clock period. In the event of a disturbing signal near or even at this particular point in time there is a significant distortion of the output signal of the DUT, and the clocked comparator may come to an incorrect bit level evaluation.